Silicon wafer is thin slice of single crystal Silicon. Crystalline silicon has a complete periodic lattice structure and is a good semiconducting material. Its different crystal directions shows unique properties. Purity requirements of Silicon wafer for research and Industrial application must be 99.99%. Not just material purity but for semiconductor device fabrication, deviation from specification should be minimum. You can read about various Silicon wafer quality grades in the following link:CLICK HERE.
We provide Prime grade (lower grades can also be supplied on special request) monocrystalline Silicon, Silicon dioxide on Silicon (grown by thermal oxidation), Silicon Nitride on Silicon (Si3N4:grown by LPCVD) and Silicon on insulator (SOI) wafers. Monocystalline Silicon ingots are manufactured by either Czochralski (CZ) or Float Zone (FZ) method resulting in a excellent quality and high purity. A Silicon wafer is obtained from wire cutting of Silicon ingot followed by polishing and cleaning. Both Doped and Undoped wafers are available. Resistivity or doping concentration or doping type (P/N type Si wafer), Orientation, thickness of the wafer can be customized as per your requirement.
Substrate for PVD / CVD coating, magnetron sputtering, molecular beam epitaxy, sample for atomic force growth, infrared spectroscopy, fluorescence spectroscopy and in manufacturing NEMS/MEMES/integrated circuits.
|Diameter||inches||2 inch or 3 inch or 4 inch or 6 inch or 8 inch|
|Diameter||mm||50.8±0.3 or 76.2±0.3 or 100±0.5 or 154±0.5 or 200±0.5|
|Growth Method||CZ / FZ|
|Dopant||Boron / Phosphorus|
|Type||P / N type|
|Thickness||μm||180 – 1000±10 or as required|
|Orientation||<100> <110> <111>±1|
|Polishing||Single side or Double side polished|
|SiO2 layer (grown by thermal oxidation) / Si3N4 layer (grown by LPCVD)||layer thickness as required|
|Packing||As per requirement|
Silicon on Insulator (SOI) wafers are widely used in manufacturing complementary metal oxide semiconductors (CMOS) and microelectromechanical systems (MEMS). SOI wafers offer advantage of high speed and low power or heat dissipation over Si wafer. SOI wafer consists of three stacked layers: Active device layer of prime grade Silicon, insulting SiO2 buried oxide layer and Silicon handle layer. Schematics of SOI wafer is shown below:
|Diameter||4 Inches or 6 Inches 8 Inches|
|Device thickness||2 um to 300 um|
|Orientation||<100> or <111> or <110> or others|
|Conductivity||P - type or N - type or Intrinsic|
|Resistivity||0.001 to 100000 ohm-cm|
|Oxide thickness||500A to 4 um|
|Handle wafer||>= 300 um|
|Surface||Double sides polished|